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-- Testbench for the 3 to 8 decoder.

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library IEEE;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_1164.all;

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entity DECODE_TB is
end DECODE_TB;

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architecture TB of DECODE_TB is

    signal input : UNSIGNED (2 downto 0) := "000";
    signal output: UNSIGNED(7 downto 0);

    component DECODE 
      port( input  : in    UNSIGNED(2 downto 0);
            output : out   UNSIGNED(7 downto 0) );
    end component;

begin

    U_DECODE : DECODE port map (input, output);

    process
    begin

	-- Case "000"
	wait for 10 ns;
	input <= "000";
	wait for 1 ns;
	assert (output = 1 ) report "Error Case 0" severity error;

	-- Case "001"
	wait for 10 ns;
	input <= "001";
	wait for 1 ns;
	assert (output = 2 ) report "Error Case 1" severity error;

	-- Case "010"
	wait for 10 ns;
	input <= "010";
	wait for 1 ns;
	assert (output = 4 ) report "Error Case 2" severity error;

	-- Case "011"
	wait for 10 ns;
	input <= "011";
	wait for 1 ns;
	assert (output <= 8 ) report "Error Case 3" severity error;

	-- Case "100"
	wait for 10 ns;
	input <= "100";
	wait for 1 ns;
	assert (output <= 16 ) report "Error Case 4" severity error;

	-- Case "101"
	wait for 10 ns;
	input <= "101";
	wait for 1 ns;
	assert (output <= 32 ) report "Error Case 5" severity error;

	-- Case "110"
	wait for 10 ns;
	input <= "110";
	wait for 1 ns;
	assert (output <= 64 ) report "Error Case 6" severity error;

	-- Case "111"
	wait for 10 ns;
	input <= "111";
	wait for 1 ns;
	assert (output = 128 ) report "Error Case 7" severity error;

	end process;

end TB;

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configuration CFG_TB of DECODE_TB is
	for TB
	end for;
end CFG_TB;

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