VHDL Verification Course

Recommended Directory Structure

It's useful to have a standardized directory structure for every module in an ASIC project. It makes it easier for designers to understand each others code and scripts can be shared more easily.

Below is a recommended directory structure which works well for the author. Many other structures are of course just as useful. (Instead of module the name of the module should be used.)

Directory Contents

bin Scripts for running tests

doc Module documentation

sim Simulation directory,
contains the VHDL work library, simulator setup files,
current transaction log etc

synth Synthesis directory,
contains the work directory for intermediate files of the synthesis tool,
synthesis scripts, constraint files

tbench VHDL testbench code

test Test case directory,
contains a directory for each test that is run with the following subdirectories
cmd: command files, any files which are required to run the test
exp: expected (golden) log files to compare the results with
res: result files of the last simulation run

vhdl VHDL design code (synthesizable VHDL)

Directory	Contents
bin	Scripts for running tests
doc	Module documentation
sim	Simulation directory, contains the VHDL work library, simulator setup files, current transaction log etc
synth	Synthesis directory, contains the work directory for intermediate files of the synthesis tool, synthesis scripts, constraint files
tbench	VHDL testbench code
test	Test case directory, contains a directory for each test that is run with the following subdirectories cmd: command files, any files which are required to run the test exp: expected (golden) log files to compare the results with res: result files of the last simulation run
vhdl	VHDL design code (synthesizable VHDL)