read -format vhdl FIR.vhd

current_design = FIR_filter

create_clock -name clock -period 17.0 clk
set_input_delay 2.0 -clock clock rst
set_input_delay 2.0 -clock clock coef_ld
set_input_delay 2.0 -clock clock start
set_input_delay 2.0 -clock clock o_enable
set_input_delay 2.0 -clock clock bypass
set_input_delay 2.0 -clock clock Xn_in
set_input_delay 2.0 -clock clock Yn_in
set_output_delay 2.0 -clock clock Xn_out
set_output_delay 2.0 -clock clock Yn_out

set_max_area 5000

compile -map_effort high -incremental_mapping

vhdlout_architecture_name="SYN"
vhdlout_use_packages={"IEEE.std_logic_1164","IEEE.std_logic_arith.all","IEEE.std_logic_textio.all","lsi_10k.COMPONENTS.all"}

write -f vhdl -hierarchy -output "FIR_gate.vhd"
write -f db -hierarchy -output "FIR_gate.db"

report_timing -path full -delay max -max_paths 1 -nworst 1
report_area

quit