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-- UART Modeling: Receiver Part
--
-- Test Bench #2 for UART Receiver
-- by: Weijun Zhang, 05/2001
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.my_package.all;

entity test2_recei is
end test2_recei;

architecture bench2 of test2_recei is

component recei is
port(	RRC:		in std_logic;
	MR:		in std_logic;
	RRI:		in std_logic;
	SFD:		in std_logic;
	RRD:		in std_logic;					
	DRR:		in std_logic;
	CRL:		in std_logic;
	CTRLWORD:	in std_logic_vector(4 downto 0);
	OE:		out std_logic;				
	PE:		out std_logic;
	FE:		out std_logic;
	DR:		out std_logic;
	RBR:		out std_logic_vector(7 downto 0)
);			  
end component;

signal T_RRC,T_MR,T_RRI,T_SFD,T_RRD,T_DRR,T_CRL: std_logic;
signal T_OE,T_PE,T_FE,T_DR: std_logic;
signal T_RBR: std_logic_vector(7 downto 0);
signal T_CTRLWORD: std_logic_vector(4 downto 0);

begin
	
Unit: recei port map(	T_RRC,T_MR,T_RRI,T_SFD,T_RRD,T_DRR,T_CRL, 
			T_CTRLWORD,T_OE,T_PE,T_FE,T_DR,T_RBR);

clk_sig: process
begin
	T_RRC <='1';
	wait for 5 ns;
	T_RRC <= '0';
	wait for 5 ns;
end process;

process
begin
	T_MR <= '1';		-- initialization...
	T_CRL <= '1';
	T_CTRLWORD <= "11000";
	T_DRR <= '1';
	T_RRD <= '0';
	T_RRI <= '0';
	T_SFD <= '0';
	wait for 100 ns;
	
	T_CRL <= '0';		-- load ctrl word here
	wait for 60 ns;
	
	T_MR <= '0'; 		-- 1 start bit of data #1
	wait for 160 ns;
	T_RRI <= '1';
	wait for 160 ns;
	T_RRI <= '0';
	wait for 320 ns;
	T_RRI <= '1';
	wait for 480 ns;
	T_RRI <= '0';		    	
	wait for 160 ns;
	T_RRI <= '1';		    	 
	wait for 160 ns;
	T_RRI <= '0';
	wait for 160 ns;
	T_RRI <= '1';	    	-- 1 stop bit
	wait for 160 ns;
	
	wait for 320 ns;	-- sencond data coming...
	T_RRI <= '0';						 
	
	wait for 160 ns;
	T_DRR <= '0';
	wait for 360 ns;
	T_DRR <= '1';
	
	wait for 160 ns;	-- test function of SFD and RRD
	T_SFD <= '1';
	wait for 160 ns;
	T_RRD <= '1';
	
	wait;
	
end process;
end bench2;

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configuration CFG_TB of test2_recei is
	for bench2
	end for;
end CFG_TB;
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