library IEEE;

use IEEE.std_logic_1164.all;

package CONV_PACK_BRIDGE is

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_BRIDGE;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_BRIDGE.all;

entity BRIDGE is

   port( clock, reset, rdy_in : in std_logic;  data_in : in std_logic_vector (3
         downto 0);  rdy_out : out std_logic;  data_out : out std_logic_vector 
         (7 downto 0));

end BRIDGE;

architecture SYN_struct of BRIDGE is

   component controller
      port( ctrl_clk, ctrl_rst, sig_in : in std_logic;  data_lo_ld, data_hi_ld,
            data_out_ld, sig_out : out std_logic);
   end component;
   
   component registers_n4
      port( clk, rst, ld : in std_logic;  reg_in : in std_logic_vector (0 to 3)
            ;  reg_out : out std_logic_vector (0 to 3));
   end component;
   
   component registers_n8
      port( clk, rst, ld : in std_logic;  reg_in : in std_logic_vector (0 to 7)
            ;  reg_out : out std_logic_vector (0 to 7));
   end component;
   
   signal wire2, connection_4_port, connection_0_port, wire0, wire1, 
      connection_6_port, connection_2_port, connection_7_port, 
      connection_3_port, connection_1_port, connection_5_port : std_logic;

begin
   
   CTRL : controller port map( ctrl_clk => clock, ctrl_rst => reset, sig_in => 
                           rdy_in, data_lo_ld => wire0, data_hi_ld => wire1, 
                           data_out_ld => wire2, sig_out => rdy_out);
   SREG_2 : registers_n4 port map( clk => clock, rst => reset, ld => wire0, 
                           reg_in(0) => data_in(3), reg_in(1) => data_in(2), 
                           reg_in(2) => data_in(1), reg_in(3) => data_in(0), 
                           reg_out(0) => connection_3_port, reg_out(1) => 
                           connection_2_port, reg_out(2) => connection_1_port, 
                           reg_out(3) => connection_0_port);
   SREG_1 : registers_n4 port map( clk => clock, rst => reset, ld => wire1, 
                           reg_in(0) => data_in(3), reg_in(1) => data_in(2), 
                           reg_in(2) => data_in(1), reg_in(3) => data_in(0), 
                           reg_out(0) => connection_7_port, reg_out(1) => 
                           connection_6_port, reg_out(2) => connection_5_port, 
                           reg_out(3) => connection_4_port);
   BREG : registers_n8 port map( clk => clock, rst => reset, ld => wire2, 
                           reg_in(0) => connection_7_port, reg_in(1) => 
                           connection_6_port, reg_in(2) => connection_5_port, 
                           reg_in(3) => connection_4_port, reg_in(4) => 
                           connection_3_port, reg_in(5) => connection_2_port, 
                           reg_in(6) => connection_1_port, reg_in(7) => 
                           connection_0_port, reg_out(0) => data_out(7), 
                           reg_out(1) => data_out(6), reg_out(2) => data_out(5)
                           , reg_out(3) => data_out(4), reg_out(4) => 
                           data_out(3), reg_out(5) => data_out(2), reg_out(6) 
                           => data_out(1), reg_out(7) => data_out(0));

end SYN_struct;