library IEEE,lsi_10k;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;

package CONV_PACK_counter is

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_counter;

library IEEE,lsi_10k;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;

use work.CONV_PACK_counter.all;

entity counter is

   generic( n : Integer := 2);
   port( clock, clear, count : in std_logic;  Q : out std_logic_vector (1 
         downto 0));

end counter;

architecture SYN of counter is

   component IV
      port( A : in std_logic;  Z : out std_logic);
   end component;
   
   component EO
      port( A, B : in std_logic;  Z : out std_logic);
   end component;
   
   component ND2
      port( A, B : in std_logic;  Z : out std_logic);
   end component;
   
   component FD2
      port( D, CP, CD : in std_logic;  Q, QN : out std_logic);
   end component;
   
   signal Q_1_port, Q_0_port, n149, n150, net9, n151, n152, n153 : std_logic;

begin
   Q <= ( Q_1_port, Q_0_port );
   
   U31 : IV port map( A => clear, Z => n150);
   U32 : EO port map( A => Q_0_port, B => count, Z => n152);
   U33 : EO port map( A => n149, B => net9, Z => n151);
   U34 : ND2 port map( A => count, B => Q_0_port, Z => n149);
   Pre_Q_regx1x : FD2 port map( D => n151, CP => clock, CD => n150, Q => 
                           Q_1_port, QN => net9);
   Pre_Q_regx0x : FD2 port map( D => n152, CP => clock, CD => n150, Q => 
                           Q_0_port, QN => n153);

end SYN;