read -format vhdl counter.vhd

current_design = counter

create_clock -name clock -period 10.0 clock
set_input_delay 2.0 -clock clock clear
set_input_delay 2.0 -clock clock count
set_output_delay 3.0 -clock clock Q

compile -map_effort medium -incremental_mapping

vhdlout_architecture_name="SYN"
vhdlout_use_packages={"IEEE.std_logic_1164","IEEE.std_logic_arith.all","IEEE.std_logic_textio.all","lsi_10k.COMPONENTS.all"}

write -f vhdl -hierarchy -output "counter_gate.vhd"
write -f db -hierachy -output "counter_gate.db"

report_timing -path full -delay max -max_paths 1 -nworst 1

quit