library IEEE,lsi_10k;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;

package CONV_PACK_dff is

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_dff;

library IEEE,lsi_10k;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;

use work.CONV_PACK_dff.all;

entity dff is

   port( data_in, clock : in std_logic;  data_out : out std_logic);

end dff;

architecture SYN of dff is

   component FD1P
      port( D, CP : in std_logic;  Q, QN : out std_logic);
   end component;
   
   signal n15 : std_logic;

begin
   
   data_out_reg : FD1P port map( D => data_in, CP => clock, Q => data_out, QN 
                           => n15);

end SYN;