library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; package CONV_PACK_seq_design is -- define attributes attribute ENUM_ENCODING : STRING; end CONV_PACK_seq_design; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_seq_design.all; entity seq_design is port( a, clock, reset : in std_logic; x : out std_logic); end seq_design; architecture SYN of seq_design is component AN2 port( A, B : in std_logic; Z : out std_logic); end component; component EN port( A, B : in std_logic; Z : out std_logic); end component; component EO port( A, B : in std_logic; Z : out std_logic); end component; component ND2 port( A, B : in std_logic; Z : out std_logic); end component; component FD2P port( D, CP, CD : in std_logic; Q, QN : out std_logic); end component; component IVA port( A : in std_logic; Z : out std_logic); end component; signal next_state_1_port, next_state_0_port, current_state_1_port, current_state_0_port, n47, n48, n49, n50 : std_logic; begin U22 : AN2 port map( A => current_state_0_port, B => current_state_1_port, Z => x); U23 : EN port map( A => n47, B => current_state_1_port, Z => next_state_1_port); U24 : EO port map( A => a, B => current_state_0_port, Z => next_state_0_port ); U25 : ND2 port map( A => a, B => current_state_0_port, Z => n47); current_state_regx0x : FD2P port map( D => next_state_0_port, CP => clock, CD => n48, Q => current_state_0_port, QN => n49); current_state_regx1x : FD2P port map( D => next_state_1_port, CP => clock, CD => n48, Q => current_state_1_port, QN => n50); U26 : IVA port map( A => reset, Z => n48); end SYN;