library IEEE;

use IEEE.std_logic_1164.all;

package CONV_PACK_gcd is

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_gcd;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_gcd.all;

entity gcd is

   port( rst, clk, go_i : in std_logic;  x_i, y_i : in std_logic_vector (3 
         downto 0);  d_o : out std_logic_vector (3 downto 0));

end gcd;

architecture SYN_gcd_arc of gcd is

   component fsm
      port( rst, clk, proceed : in std_logic;  comparison : in std_logic_vector
            (0 to 1);  enable, xsel, ysel, xld, yld : out std_logic);
   end component;
   
   component mux
      port( rst, sLine : in std_logic;  load, result : in std_logic_vector (0 
            to 3);  output : out std_logic_vector (0 to 3));
   end component;
   
   component regis
      port( rst, clk, load : in std_logic;  input : in std_logic_vector (0 to 
            3);  output : out std_logic_vector (0 to 3));
   end component;
   
   component comparator
      port( rst : in std_logic;  x, y : in std_logic_vector (0 to 3);  output :
            out std_logic_vector (0 to 1));
   end component;
   
   component subtractor
      port( rst : in std_logic;  cmd : in std_logic_vector (0 to 1);  x, y : in
            std_logic_vector (0 to 3);  xout, yout : out std_logic_vector (0 to
            3));
   end component;
   
   signal comparison_0_port, yreg_2_port, xreg_2_port, xreg_0_port, yreg_0_port
      , enable, xsub_1_port, ymux_3_port, xld, yld, xmux_3_port, ysub_3_port, 
      ysub_1_port, xmux_1_port, xsub_3_port, ymux_1_port, xsub_2_port, 
      ymux_0_port, ysub_2_port, comparison_1_port, xsel, xmux_2_port, 
      xmux_0_port, ysel, xsub_0_port, ysub_0_port, ymux_2_port, yreg_1_port, 
      xreg_3_port, xreg_1_port, yreg_3_port : std_logic;

begin
   
   TOFSM : fsm port map( rst => rst, clk => clk, proceed => go_i, comparison(0)
                           => comparison_1_port, comparison(1) => 
                           comparison_0_port, enable => enable, xsel => xsel, 
                           ysel => ysel, xld => xld, yld => yld);
   X_MUX : mux port map( rst => rst, sLine => xsel, load(0) => x_i(3), load(1) 
                           => x_i(2), load(2) => x_i(1), load(3) => x_i(0), 
                           result(0) => xsub_3_port, result(1) => xsub_2_port, 
                           result(2) => xsub_1_port, result(3) => xsub_0_port, 
                           output(0) => xmux_3_port, output(1) => xmux_2_port, 
                           output(2) => xmux_1_port, output(3) => xmux_0_port);
   OUT_REG : regis port map( rst => rst, clk => clk, load => enable, input(0) 
                           => xsub_3_port, input(1) => xsub_2_port, input(2) =>
                           xsub_1_port, input(3) => xsub_0_port, output(0) => 
                           d_o(3), output(1) => d_o(2), output(2) => d_o(1), 
                           output(3) => d_o(0));
   Y_MUX : mux port map( rst => rst, sLine => ysel, load(0) => y_i(3), load(1) 
                           => y_i(2), load(2) => y_i(1), load(3) => y_i(0), 
                           result(0) => ysub_3_port, result(1) => ysub_2_port, 
                           result(2) => ysub_1_port, result(3) => ysub_0_port, 
                           output(0) => ymux_3_port, output(1) => ymux_2_port, 
                           output(2) => ymux_1_port, output(3) => ymux_0_port);
   X_REG : regis port map( rst => rst, clk => clk, load => xld, input(0) => 
                           xmux_3_port, input(1) => xmux_2_port, input(2) => 
                           xmux_1_port, input(3) => xmux_0_port, output(0) => 
                           xreg_3_port, output(1) => xreg_2_port, output(2) => 
                           xreg_1_port, output(3) => xreg_0_port);
   U_COMP : comparator port map( rst => rst, x(0) => xreg_3_port, x(1) => 
                           xreg_2_port, x(2) => xreg_1_port, x(3) => 
                           xreg_0_port, y(0) => yreg_3_port, y(1) => 
                           yreg_2_port, y(2) => yreg_1_port, y(3) => 
                           yreg_0_port, output(0) => comparison_1_port, 
                           output(1) => comparison_0_port);
   X_SUB : subtractor port map( rst => rst, cmd(0) => comparison_1_port, cmd(1)
                           => comparison_0_port, x(0) => xreg_3_port, x(1) => 
                           xreg_2_port, x(2) => xreg_1_port, x(3) => 
                           xreg_0_port, y(0) => yreg_3_port, y(1) => 
                           yreg_2_port, y(2) => yreg_1_port, y(3) => 
                           yreg_0_port, xout(0) => xsub_3_port, xout(1) => 
                           xsub_2_port, xout(2) => xsub_1_port, xout(3) => 
                           xsub_0_port, yout(0) => ysub_3_port, yout(1) => 
                           ysub_2_port, yout(2) => ysub_1_port, yout(3) => 
                           ysub_0_port);
   Y_REG : regis port map( rst => rst, clk => clk, load => yld, input(0) => 
                           ymux_3_port, input(1) => ymux_2_port, input(2) => 
                           ymux_1_port, input(3) => ymux_0_port, output(0) => 
                           yreg_3_port, output(1) => yreg_2_port, output(2) => 
                           yreg_1_port, output(3) => yreg_0_port);

end SYN_gcd_arc;