library IEEE,lsi_10k;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;

package CONV_PACK_JK_FF is

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_JK_FF;

library IEEE,lsi_10k;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;

use work.CONV_PACK_JK_FF.all;

entity JK_FF is

   port( clock, J, K, reset : in std_logic;  Q, Qbar : out std_logic);

end JK_FF;

architecture SYN of JK_FF is

   component FJK2P
      port( J, K, CP, CD : in std_logic;  Q, QN : out std_logic);
   end component;
   
   component IVA
      port( A : in std_logic;  Z : out std_logic);
   end component;
   
   signal n45 : std_logic;

begin
   
   state_reg : FJK2P port map( J => J, K => K, CP => clock, CD => n45, Q => Q, 
                           QN => Qbar);
   U23 : IVA port map( A => reset, Z => n45);

end SYN;