library IEEE,lsi_10k;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;

package CONV_PACK_reg is

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_reg;

library IEEE,lsi_10k;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;

use work.CONV_PACK_reg.all;

entity reg is

   port( I : in std_logic_vector (1 downto 0);  clock, load, clear : in 
         std_logic;  Q : out std_logic_vector (1 downto 0));

end reg;

architecture SYN of reg is

   component FJK2SP
      port( J, K, CP, CD, TI, TE : in std_logic;  Q, QN : out std_logic);
   end component;
   
   signal n50, n51, n52, n53 : std_logic;

begin
   
   Q_regx1x : FJK2SP port map( J => n50, K => n50, CP => clock, CD => clear, TI
                           => I(1), TE => load, Q => Q(1), QN => n52);
   n50 <= '0';
   Q_regx0x : FJK2SP port map( J => n51, K => n51, CP => clock, CD => clear, TI
                           => I(0), TE => load, Q => Q(0), QN => n53);
   n51 <= '0';

end SYN;