library IEEE,lsi_10k;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;

package CONV_PACK_shift_reg is

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_shift_reg;

library IEEE,lsi_10k;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;

use work.CONV_PACK_shift_reg.all;

entity shift_reg is

   generic( n : Integer := 3);
   port( I, clock, shift : in std_logic;  Q : out std_logic);

end shift_reg;

architecture SYN of shift_reg is

   component FDS2LP
      port( D, CP, CR, LD : in std_logic;  Q, QN : out std_logic);
   end component;
   
   signal Sx2x, Sx1x, n19, n20, n21, n22, n23, n24 : std_logic;

begin
   
   S_regx2x : FDS2LP port map( D => I, CP => clock, CR => n19, LD => shift, Q 
                           => Sx2x, QN => n22);
   n19 <= '1';
   S_regx1x : FDS2LP port map( D => Sx2x, CP => clock, CR => n20, LD => shift, 
                           Q => Sx1x, QN => n23);
   n20 <= '1';
   S_regx0x : FDS2LP port map( D => Sx1x, CP => clock, CR => n21, LD => shift, 
                           Q => Q, QN => n24);
   n21 <= '1';

end SYN;