--------------------------------------------------------------------------
-- Test Bench for FIR digital filter design
-- by Weijun Zhang, 04/2001
--------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;  
use ieee.std_logic_arith.all;	   
use ieee.std_logic_unsigned.all;

entity FIR_TB is
end FIR_TB;

--------------------------------------------------------------------------

architecture TB of FIR_TB is

    signal T_rst, T_clk: 	std_logic;
    signal T_coef_ld:		std_logic;
    signal T_start:		std_logic;
    signal T_o_enable:		std_logic; 
    signal T_bypass:		std_logic;
    signal T_Xn_in:		std_logic_vector(3 downto 0);
    signal T_Yn_in:		std_logic_vector(15 downto 0);
    signal T_Xn_out:		std_logic_vector(3 downto 0);
    signal T_Yn_out:		std_logic_vector(15 downto 0);
	
    component FIR_filter is
    port(	rst:		in	std_logic;
		clk:		in	std_logic;
		coef_ld:	in	std_logic;
		start:		in	std_logic;
		o_enable:	in	std_logic;
		bypass:		in	std_logic;
		Xn_in:		in 	std_logic_vector(3 downto 0);
		Yn_in:		in	std_logic_vector(15 downto 0);
		Xn_out:		out	std_logic_vector(3 downto 0);
		Yn_out:		out	std_logic_vector(15 downto 0)
    );
    end component;
		
    begin
    
    Unit: FIR_filter port map (	T_rst, T_clk, T_coef_ld, T_start, 
				T_o_enable, T_bypass, T_Xn_in, 
				T_Yn_in, T_Xn_out, T_Yn_out);
	
    process
    begin
	T_clk <= '0';				-- offer clock signal
	wait for 5 ns;				-- in cocurrent process
	T_clk <= '1';
	wait for 5 ns;
    end process;
	
    process
    begin
		
	T_rst <= '0';				-- initialization
	T_coef_ld <= '0';
	T_start <= '0';
	T_o_enable <= '0';
	T_bypass <= '0';
	T_Xn_in <= "0000";
	T_Yn_in <= "0000000000000000";
	wait for 20 ns;
		
	T_rst <= '1';				-- reset the circuit
	wait for 20 ns;
		
	T_coef_ld <= '1';			-- load 4 coeficients
	T_Xn_in <= "0001";
	wait for 40 ns;
		
	T_coef_ld <= '0';
	T_Xn_in <= "0000";
	wait for 20 ns;
		
	T_start <= '1';	 			-- start computation
	wait for 20 ns;
	T_Xn_in <= "0001";
				
	for i in 0 to 14 loop			-- feed different inputs
	    wait for 10 ns;
	    T_Xn_in <= T_Xn_in + '1';	   
	end loop;
		
	wait for 20 ns;				-- output high resistance
	T_o_enable <= '1';
		
	wait for 40 ns;		
	T_o_enable <= '0';
		
	wait for 20 ns;				-- bypass the circuit
	T_bypass <= '1';
		
	wait;

    end process;

end TB;

---------------------------------------------------------------------------

configuration CFG_TB of FIR_TB is
	for TB
	end for;
end CFG_TB;

----------------------------------------------------------------------------