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-- Test Bench for ISA bus controller
-- by Weijun Zhang, 05/2001
----------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;  
use ieee.std_logic_arith.all;	   

entity ISA_TB is
end ISA_TB;

architecture TB of ISA_TB is

    component ISA is
    port(	CLK_P:		in std_logic;
		RESET_P:	in std_logic;
		IOR_P:		in std_logic;
		IOW_P:		in std_logic;
		ALE_P:		in std_logic;
		ADDRESS_P:	in std_logic_vector(15 downto 0);
		DIN_P:		in std_logic_vector(7 downto 0);
		DOUT_P:		out std_logic_vector(7 downto 0)
    );
    end component;
	
    signal T_CLK_P, T_RESET_P, T_IOR_P, T_IOW_P, T_ALE_P: std_logic;
    signal T_ADDRESS_P: std_logic_vector(15 downto 0);
    signal T_DIN_P: std_logic_vector(7 downto 0);
    signal T_DOUT_P: std_logic_vector(7 downto 0);
	
begin
	
    UUT: ISA port map (	T_CLK_P,T_RESET_P,T_IOR_P,T_IOW_P,
			T_ALE_P,T_ADDRESS_P,T_DIN_P,T_DOUT_P);
	
    process
    begin
	T_CLK_P <= '0';
	wait for 5 ns;
	T_CLK_P <= '1';
	wait for 5 ns;
    end process;
	
    process
    begin
	
	T_RESET_P <= '1';			-- initialization
	T_ALE_P <= '0';
	T_IOR_P <= '1';
	T_IOW_P <= '1';
	T_ADDRESS_P <= "0000000000000000";
	T_DIN_P <= "ZZZZZZZZ";
	wait for 20 ns;
		
	T_RESET_P <= '0';			-- starting point
	wait for 20 ns;
		
	T_ALE_P <= '1';				-- assert ALE
	T_ADDRESS_P <= "1010000000000000";	-- offer Writing Address
	wait for 20 ns;
		
	T_IOW_P <= '0';				-- release ALE, assert IOW 
	T_ALE_P <= '0';				-- prepare data
	T_DIN_P <= "00110011";
	wait for 40 ns;
		
	T_IOW_P <= '1';				-- finish writing	  
	T_DIN_P <= "ZZZZZZZZ";
	wait for 30 ns;
		
	T_ALE_P <= '1';				-- assert ALE
	T_ADDRESS_P <= "1010000000000001";	-- offer Reading Address
	wait for 20 ns;
		
	T_IOR_P <= '0';				-- release ALE, assert IOR 
	T_ALE_P <= '0';				-- prepare data
	wait for 50 ns;
		
	T_IOR_P <= '1';				-- finish writing	  
	wait;

    end process;

end TB;
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configuration CFG_TB of ISA_TB is
	for TB
	end for;
end CFG_TB;
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