---------------------------------------------------------------------------------- -- Test Bench for simple bridge (ESD book Figure 2.14) -- by Weijun Zhang, 04/2001 -- -- three cases tested ---------------------------------------------------------------------------------- Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.all; ----------------------------------------------------------------------------------- entity test_BRIDGE is end test_BRIDGE; architecture Bench of test_BRIDGE is component BRIDGE port( clock: in std_logic; reset: in std_logic; rdy_in: in std_logic; data_in: in std_logic_vector(3 downto 0); rdy_out: out std_logic; data_out: out std_logic_vector(7 downto 0) ); end component; signal T_clock,T_reset: std_logic; signal T_rdy_in, T_rdy_out: std_logic; signal T_data_in: std_logic_vector(3 downto 0); signal T_data_out: std_logic_vector(7 downto 0); begin U1: BRIDGE port map(T_clock, T_reset, T_rdy_in, T_data_in, T_rdy_out, T_data_out); Clk_sig: process begin T_clock<='1'; wait for 10 ns; T_clock<='0'; wait for 10 ns; end process; process variable err_cnt: integer := 0; begin T_reset <= '1'; T_data_in <= "1010"; T_rdy_in <= '0'; wait for 50 ns; -- case 1 T_reset <= '0'; wait for 50 ns; assert(T_data_out="00000000") report "Test Failed!" severity error; if (T_data_out/="00000000") then err_cnt := err_cnt + 1; end if; T_rdy_in <= '1'; wait for 100 ns; -- case 2 T_rdy_in <= '0'; T_data_in <= "0010"; wait for 50 ns; assert(T_data_out="00000000") report "Test Failed!" severity error; if (T_data_out/="0000000") then err_cnt := err_cnt + 1; end if; T_rdy_in <= '1'; wait for 100 ns; -- case 3 T_rdy_in <= '0'; wait for 200 ns; assert (T_data_out="00101010") report "Test failed!" severity error; if (T_data_out/="00000000") then err_cnt := err_cnt + 1; end if; -- summary of all the tests if (err_cnt=0) then assert false report "Testbench of Adder completed successfully!" severity note; else assert true report "Something wrong, try again" severity error; end if; wait; end process; end Bench; ------------------------------------------------------------------------------------- configuration CFG_TB of test_BRIDGE is for Bench end for; end CFG_TB; -------------------------------------------------------------------------------------