library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; package CONV_PACK_trans is -- define attributes attribute ENUM_ENCODING : STRING; end CONV_PACK_trans; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_trans.all; entity trans is port( TRC, MR, TBRL, SFD, CRL : in std_logic; CTRLWORD : in std_logic_vector (4 downto 0); TBR : in std_logic_vector (7 downto 0) ; TRE, TBRE, TRO : out std_logic); end trans; architecture SYN of trans is component ND4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component ND3 port( A, B, C : in std_logic; Z : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component AO7 port( A, B, C : in std_logic; Z : out std_logic); end component; component ND2 port( A, B : in std_logic; Z : out std_logic); end component; component OR2 port( A, B : in std_logic; Z : out std_logic); end component; component AO3 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component AN2 port( A, B : in std_logic; Z : out std_logic); end component; component AN3 port( A, B, C : in std_logic; Z : out std_logic); end component; component OR4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component EN port( A, B : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component OR3 port( A, B, C : in std_logic; Z : out std_logic); end component; component NR4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component EO port( A, B : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component NR3 port( A, B, C : in std_logic; Z : out std_logic); end component; component AO6 port( A, B, C : in std_logic; Z : out std_logic); end component; component EO1 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component BTS4P port( A, E : in std_logic; Z : out std_logic); end component; component LD1P port( D, G : in std_logic; Q, QN : out std_logic); end component; component LD2P port( D, GN : in std_logic; Q, QN : out std_logic); end component; component FDS2LP port( D, CP, CR, LD : in std_logic; Q, QN : out std_logic); end component; component FD1P port( D, CP : in std_logic; Q, QN : out std_logic); end component; component FJK1P port( J, K, CP : in std_logic; Q, QN : out std_logic); end component; component LD4P port( D, GN, CD : in std_logic; Q, QN : out std_logic); end component; component IVA port( A : in std_logic; Z : out std_logic); end component; component HA1P port( A, B : in std_logic; S, CO : out std_logic); end component; signal sum1616x2x, temp391, ix2x, cntx0x, cnt_limit1021x3x, cnt_limit1021x1x , go, trans_reg903x10x, ix0x, cntx2x, TBR_sig_2_port, ARG1440x2x, ctrl_word_2_port, old_tbr_sig745x1x, TBR_sig157x1x, trans_reg903x5x, TBR_sig_6_port, old_tbr_sig745x5x, trans_reg903x8x, trans_reg903x1x, cnt716x3x, TBR_sig157x5x, i773x0x, cnt716x1x, TBR_sig157x7x, i773x2x, trans_reg903x3x, TBR_sig_4_port, ctrl_word_4_port, old_tbr_sig745x7x, trans_reg903x7x, TBR_sig157x3x, old_tbr_sig745x3x, TBR_sig_0_port, ctrl_word_0_port, TBRE_Q817, trans_reg903x6x, TBR_sig157x2x, old_tbr_sig745x2x, ARG1440x1x, TBR_sig_1_port, ctrl_word_1_port, cnt716x0x, i773x3x, TBR_sig157x6x, trans_reg903x2x, n880, n781x3x, TBR_sig_5_port, old_tbr_sig745x6x, delayx0x, n790, old_tbr_sig745x4x, n746x0x, trans_reg903x9x, TBR_sig_7_port, trans_reg903x0x, cnt716x2x, TBR_sig157x4x, i773x1x, TBR_sig_3_port, ctrl_word_3_port, old_tbr_sig745x0x, TBR_sig157x0x, trans_reg903x4x, sum1616x1x, TRE897, cnt_limit1021x0x, ix1x, cntx3x, ix3x, cntx1x, cnt_limit1021x2x, t_pari, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, r107xcarryx2x, r107xcarryx3x, P3xadd_254xplusxcarryx2x, P3xadd_254xplusxcarryx3x, xcellx170xU33xDATA2_0, xcellx170xU31xDATA2_0, xcellx170xU29xDATA2_0, xcellx170xU11xCONTROL2, n2062, n2063, n2064, n2065 , n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108 : std_logic; begin U505 : ND4 port map( A => n1900, B => n1901, C => n1902, D => n1903, Z => cnt_limit1021x3x); U506 : ND3 port map( A => n1904, B => n1905, C => n1906, Z => cnt_limit1021x1x); U507 : NR2 port map( A => n1908, B => n1909, Z => n1907); U508 : AO7 port map( A => n1910, B => n1911, C => go, Z => cnt716x3x); U509 : ND2 port map( A => go, B => n1912, Z => cnt716x2x); U510 : OR2 port map( A => n1913, B => TBR_sig_7_port, Z => old_tbr_sig745x7x ); U511 : ND2 port map( A => n2060, B => n1914, Z => old_tbr_sig745x6x); U512 : ND2 port map( A => n2060, B => n1915, Z => old_tbr_sig745x5x); U513 : OR2 port map( A => n1913, B => TBR_sig_4_port, Z => old_tbr_sig745x4x ); U514 : OR2 port map( A => n1913, B => TBR_sig_3_port, Z => old_tbr_sig745x3x ); U515 : OR2 port map( A => n1913, B => TBR_sig_2_port, Z => old_tbr_sig745x2x ); U516 : OR2 port map( A => n1913, B => TBR_sig_1_port, Z => old_tbr_sig745x1x ); U517 : OR2 port map( A => n1913, B => TBR_sig_0_port, Z => old_tbr_sig745x0x ); U518 : AO7 port map( A => n1916, B => n1917, C => n2060, Z => n746x0x); U519 : NR2 port map( A => n1918, B => n1919, Z => i773x3x); U520 : NR2 port map( A => n1920, B => n1919, Z => i773x2x); U521 : NR2 port map( A => n1921, B => n1919, Z => i773x1x); U522 : NR2 port map( A => ix0x, B => n1919, Z => i773x0x); U523 : NR2 port map( A => n1922, B => n1923, Z => n781x3x); U524 : NR2 port map( A => n1913, B => n1917, Z => n790); U525 : OR2 port map( A => n1913, B => TBR(7), Z => TBR_sig157x7x); U526 : OR2 port map( A => n1913, B => TBR(6), Z => TBR_sig157x6x); U527 : OR2 port map( A => n1913, B => TBR(5), Z => TBR_sig157x5x); U528 : OR2 port map( A => n1913, B => TBR(4), Z => TBR_sig157x4x); U529 : OR2 port map( A => n1913, B => TBR(3), Z => TBR_sig157x3x); U530 : OR2 port map( A => n1913, B => TBR(2), Z => TBR_sig157x2x); U531 : OR2 port map( A => n1913, B => TBR(1), Z => TBR_sig157x1x); U532 : OR2 port map( A => n1913, B => TBR(0), Z => TBR_sig157x0x); U533 : ND2 port map( A => n1925, B => TRE897, Z => xcellx170xU29xDATA2_0); U534 : NR2 port map( A => cntx0x, B => n1910, Z => cnt716x0x); U535 : ND2 port map( A => n1926, B => n1927, Z => TRE897); U536 : ND3 port map( A => n2035, B => n1916, C => n1926, Z => trans_reg903x10x); U537 : AO3 port map( A => n2037, B => n1924, C => n1928, D => n1929, Z => trans_reg903x9x); U538 : AO3 port map( A => n1924, B => n2039, C => n1930, D => n1929, Z => trans_reg903x8x); U539 : AO3 port map( A => n1924, B => n2041, C => n1926, D => n1931, Z => trans_reg903x7x); U540 : AO3 port map( A => n1924, B => n2043, C => n1926, D => n1932, Z => trans_reg903x6x); U541 : AO3 port map( A => n1924, B => n2045, C => n1926, D => n1933, Z => trans_reg903x5x); U542 : AO3 port map( A => n1924, B => n2047, C => n1926, D => n1934, Z => trans_reg903x4x); U543 : AO3 port map( A => n1924, B => n2049, C => n1926, D => n1935, Z => trans_reg903x3x); U544 : AO3 port map( A => n1924, B => n2051, C => n1926, D => n1936, Z => trans_reg903x2x); U545 : AO3 port map( A => n1924, B => n2053, C => n1926, D => n1937, Z => trans_reg903x1x); U546 : AO3 port map( A => n1924, B => n2055, C => n1938, D => n1926, Z => trans_reg903x0x); U547 : AN2 port map( A => TBRL, B => n2060, Z => n2061); U548 : AN3 port map( A => n1940, B => n1941, C => n1942, Z => n1939); U549 : ND4 port map( A => n1943, B => n1944, C => n1945, D => n1946, Z => n1927); U550 : NR2 port map( A => n1948, B => n1927, Z => n1947); U551 : OR4 port map( A => n1922, B => cnt716x1x, C => cnt716x2x, D => cnt716x3x, Z => xcellx170xU11xCONTROL2); U552 : EN port map( A => P3xadd_254xplusxcarryx3x, B => ix3x, Z => n1918); U553 : EN port map( A => r107xcarryx3x, B => cntx3x, Z => n1911); U554 : ND4 port map( A => delayx0x, B => n1949, C => go, D => n1950, Z => n1916); U555 : ND2 port map( A => go, B => n1925, Z => n1951); U556 : ND2 port map( A => n1926, B => n1916, Z => n1924); U557 : IV port map( A => ctrl_word_2_port, Z => n1952); U558 : IV port map( A => ctrl_word_4_port, Z => n1953); U559 : ND2 port map( A => ctrl_word_4_port, B => ctrl_word_2_port, Z => n1900); U560 : IV port map( A => ctrl_word_3_port, Z => n1954); U561 : NR2 port map( A => n1954, B => ctrl_word_4_port, Z => n1955); U562 : ND2 port map( A => n1952, B => n1954, Z => n1902); U563 : ND2 port map( A => n1957, B => n1953, Z => n1956); U564 : IV port map( A => ctrl_word_1_port, Z => n1958); U565 : ND2 port map( A => n1955, B => n1952, Z => n1959); U566 : ND2 port map( A => n1957, B => ctrl_word_4_port, Z => n1905); U567 : OR3 port map( A => n1953, B => ctrl_word_2_port, C => n1954, Z => n1901); U568 : OR3 port map( A => n1961, B => n1962, C => n1963, Z => n1960); U569 : NR2 port map( A => n1964, B => n1965, Z => n1940); U570 : NR4 port map( A => n1967, B => n1968, C => n1969, D => n1970, Z => n1966); U571 : NR2 port map( A => n1951, B => n1971, Z => n1929); U572 : IV port map( A => n2060, Z => n1913); U573 : OR3 port map( A => n1973, B => n1974, C => n1975, Z => n1972); U574 : IV port map( A => TBR_sig_6_port, Z => n1914); U575 : NR2 port map( A => n1913, B => n1916, Z => n1976); U576 : NR2 port map( A => n1916, B => n2060, Z => n1971); U577 : NR2 port map( A => n1972, B => n1960, Z => n1942); U578 : IV port map( A => TBR_sig_5_port, Z => n1915); U579 : ND4 port map( A => ix3x, B => ix2x, C => ix1x, D => ix0x, Z => n1917) ; U580 : ND2 port map( A => xcellx170xU33xDATA2_0, B => n2060, Z => n1923); U581 : ND2 port map( A => n1978, B => n1901, Z => n1977); U582 : ND2 port map( A => n2060, B => n1917, Z => n1919); U583 : EO port map( A => n1979, B => n1980, Z => temp391); U584 : EN port map( A => cntx1x, B => cnt_limit1021x1x, Z => n1945); U585 : EN port map( A => cnt_limit1021x3x, B => cntx3x, Z => n1943); U586 : AO7 port map( A => n1952, B => n1954, C => n1902, Z => n1981); U587 : OR3 port map( A => n1961, B => n1983, C => n1977, Z => n1982); U588 : ND2 port map( A => n1959, B => n1900, Z => n1984); U589 : AO2 port map( A => n1947, B => go, C => n1907, D => n1985, Z => xcellx170xU31xDATA2_0); U590 : NR3 port map( A => cntx1x, B => cntx3x, C => cntx2x, Z => n1950); U591 : NR2 port map( A => n1974, B => n1960, Z => n1986); U592 : AO6 port map( A => TBR_sig_7_port, B => n1972, C => n1961, Z => n1987 ); U593 : AO2 port map( A => n1976, B => n1988, C => n1971, D => TBR_sig_7_port , Z => n1931); U594 : AO2 port map( A => n1976, B => n1989, C => n1971, D => TBR_sig_6_port , Z => n1932); U595 : AO2 port map( A => TBR_sig_4_port, B => n1976, C => TBR_sig_5_port, D => n1971, Z => n1933); U596 : AO2 port map( A => TBR_sig_3_port, B => n1976, C => TBR_sig_4_port, D => n1971, Z => n1934); U597 : AO2 port map( A => TBR_sig_2_port, B => n1976, C => TBR_sig_3_port, D => n1971, Z => n1935); U598 : AO2 port map( A => TBR_sig_1_port, B => n1976, C => TBR_sig_2_port, D => n1971, Z => n1936); U599 : AO2 port map( A => TBR_sig_0_port, B => n1976, C => TBR_sig_1_port, D => n1971, Z => n1937); U600 : EO port map( A => TBR(2), B => TBR(7), Z => n1990); U601 : EO port map( A => TBR(1), B => TBR(0), Z => n1991); U602 : EO port map( A => n1990, B => n1991, Z => n1979); U603 : EO port map( A => TBR(6), B => TBR(3), Z => n1992); U604 : EO port map( A => TBR(5), B => TBR(4), Z => n1993); U605 : EO port map( A => n1992, B => n1993, Z => n1980); U606 : NR2 port map( A => ctrl_word_0_port, B => n1955, Z => n1903); U607 : ND4 port map( A => n1994, B => n1995, C => n1996, D => n1997, Z => n1908); U608 : ND4 port map( A => n1998, B => n1999, C => n2000, D => n2001, Z => n1909); U609 : IV port map( A => cntx0x, Z => n1949); U610 : NR2 port map( A => n1985, B => delayx0x, Z => n1948); U611 : IV port map( A => n1948, Z => n1925); U612 : IV port map( A => n1917, Z => xcellx170xU33xDATA2_0); U613 : AN2 port map( A => sum1616x1x, B => n2002, Z => cnt716x1x); U614 : IV port map( A => n1916, Z => n2003); U615 : AN3 port map( A => n1954, B => n1953, C => ctrl_word_2_port, Z => n1970); U616 : IV port map( A => n1970, Z => n1978); U617 : ND2 port map( A => n1955, B => ctrl_word_2_port, Z => n1941); U618 : NR2 port map( A => n1900, B => ctrl_word_3_port, Z => n1961); U619 : NR2 port map( A => n1954, B => n1900, Z => n1974); U620 : IV port map( A => n1974, Z => n1904); U621 : NR2 port map( A => n1956, B => ctrl_word_1_port, Z => n1968); U622 : NR2 port map( A => n1958, B => n1956, Z => n1967); U623 : NR2 port map( A => n1959, B => ctrl_word_1_port, Z => n1964); U624 : NR2 port map( A => n1959, B => n1958, Z => n1965); U625 : NR2 port map( A => n1905, B => ctrl_word_1_port, Z => n1962); U626 : NR2 port map( A => n1905, B => n1958, Z => n1963); U627 : NR2 port map( A => n1901, B => ctrl_word_1_port, Z => n1973); U628 : NR2 port map( A => n1901, B => n1958, Z => n1975); U629 : IV port map( A => n1923, Z => n880); U630 : ND4 port map( A => n2005, B => n1966, C => n1986, D => n1940, Z => n2004); U631 : ND2 port map( A => n2003, B => n2004, Z => n1928); U632 : ND4 port map( A => n2007, B => n1966, C => n1987, D => n1940, Z => n2006); U633 : ND2 port map( A => n2003, B => n2006, Z => n1930); U634 : AO3 port map( A => n1942, B => n1914, C => n1966, D => n2008, Z => n1988); U635 : AO3 port map( A => n1939, B => n1915, C => n1978, D => n2009, Z => n1989); U636 : ND2 port map( A => TBR_sig_0_port, B => n1971, Z => n1938); U637 : NR2 port map( A => n1924, B => n1927, Z => n1922); U638 : ND2 port map( A => n1916, B => n1924, Z => n2002); U639 : IV port map( A => n2002, Z => n1910); U640 : ND2 port map( A => sum1616x2x, B => n2002, Z => n1912); U641 : AO2 port map( A => cnt_limit1021x0x, B => n1949, C => n2010, D => cntx0x, Z => n1946); U642 : EN port map( A => cnt_limit1021x2x, B => cntx2x, Z => n1944); U643 : EO port map( A => TBR_sig_7_port, B => n2015, Z => n1997); U644 : EO1 port map( A => TBR_sig_6_port, B => n2017, C => TBR_sig_6_port, D => n2017, Z => n1996); U645 : EO1 port map( A => TBR_sig_5_port, B => n2019, C => TBR_sig_5_port, D => n2019, Z => n1995); U646 : EO port map( A => TBR_sig_4_port, B => n2021, Z => n1994); U647 : EO port map( A => TBR_sig_3_port, B => n2023, Z => n2001); U648 : EO port map( A => TBR_sig_2_port, B => n2025, Z => n2000); U649 : EO port map( A => TBR_sig_1_port, B => n2027, Z => n1999); U650 : EO port map( A => TBR_sig_0_port, B => n2029, Z => n1998); U651 : AO2 port map( A => n1973, B => n2011, C => n1975, D => t_pari, Z => n2005); U652 : AO2 port map( A => n1962, B => n2011, C => n1963, D => t_pari, Z => n2007); U653 : AO2 port map( A => n1964, B => n2011, C => n1965, D => t_pari, Z => n2008); U654 : AO2 port map( A => n1968, B => n2011, C => n1967, D => t_pari, Z => n2009); U655 : AO2 port map( A => n1982, B => n2012, C => n1981, D => ctrl_word_0_port, Z => n2010); U656 : AO2 port map( A => n1977, B => n2012, C => n1984, D => ctrl_word_0_port, Z => n1906); U657 : AO2 port map( A => n1978, B => n2012, C => n1901, D => ctrl_word_0_port, Z => cnt_limit1021x2x); U658 : IV port map( A => n1941, Z => n1969); U659 : IV port map( A => n1951, Z => n1926); U660 : IV port map( A => n1902, Z => n1957); U661 : IV port map( A => n1959, Z => n1983); U662 : IV port map( A => ARG1440x2x, Z => n1920); U663 : IV port map( A => ARG1440x1x, Z => n1921); U664 : IV port map( A => go, Z => n1985); U665 : IV port map( A => t_pari, Z => n2011); U666 : IV port map( A => ctrl_word_0_port, Z => n2012); U667 : IV port map( A => n2010, Z => cnt_limit1021x0x); TBRE_tri : BTS4P port map( A => TBRE_Q817, E => n2013, Z => TBRE); ctrl_word_regx4x : LD1P port map( D => CTRLWORD(4), G => CRL, Q => ctrl_word_4_port, QN => n2062); ctrl_word_regx3x : LD1P port map( D => CTRLWORD(3), G => CRL, Q => ctrl_word_3_port, QN => n2063); ctrl_word_regx2x : LD1P port map( D => CTRLWORD(2), G => CRL, Q => ctrl_word_2_port, QN => n2064); ctrl_word_regx1x : LD1P port map( D => CTRLWORD(1), G => CRL, Q => ctrl_word_1_port, QN => n2065); ctrl_word_regx0x : LD1P port map( D => CTRLWORD(0), G => CRL, Q => ctrl_word_0_port, QN => n2066); TBR_sig_regx7x : LD2P port map( D => TBR_sig157x7x, GN => n2061, Q => TBR_sig_7_port, QN => n2067); TBR_sig_regx6x : LD2P port map( D => TBR_sig157x6x, GN => n2061, Q => TBR_sig_6_port, QN => n2068); TBR_sig_regx5x : LD2P port map( D => TBR_sig157x5x, GN => n2061, Q => TBR_sig_5_port, QN => n2069); TBR_sig_regx4x : LD2P port map( D => TBR_sig157x4x, GN => n2061, Q => TBR_sig_4_port, QN => n2070); TBR_sig_regx3x : LD2P port map( D => TBR_sig157x3x, GN => n2061, Q => TBR_sig_3_port, QN => n2071); TBR_sig_regx2x : LD2P port map( D => TBR_sig157x2x, GN => n2061, Q => TBR_sig_2_port, QN => n2072); TBR_sig_regx1x : LD2P port map( D => TBR_sig157x1x, GN => n2061, Q => TBR_sig_1_port, QN => n2073); TBR_sig_regx0x : LD2P port map( D => TBR_sig157x0x, GN => n2061, Q => TBR_sig_0_port, QN => n2074); old_tbr_sig_regx7x : FDS2LP port map( D => old_tbr_sig745x7x, CP => TRC, CR => n2014, LD => n746x0x, Q => n2075, QN => n2015); n2014 <= '1'; old_tbr_sig_regx6x : FDS2LP port map( D => old_tbr_sig745x6x, CP => TRC, CR => n2016, LD => n746x0x, Q => n2076, QN => n2017); n2016 <= '1'; old_tbr_sig_regx5x : FDS2LP port map( D => old_tbr_sig745x5x, CP => TRC, CR => n2018, LD => n746x0x, Q => n2077, QN => n2019); n2018 <= '1'; old_tbr_sig_regx4x : FDS2LP port map( D => old_tbr_sig745x4x, CP => TRC, CR => n2020, LD => n746x0x, Q => n2078, QN => n2021); n2020 <= '1'; old_tbr_sig_regx3x : FDS2LP port map( D => old_tbr_sig745x3x, CP => TRC, CR => n2022, LD => n746x0x, Q => n2079, QN => n2023); n2022 <= '1'; old_tbr_sig_regx2x : FDS2LP port map( D => old_tbr_sig745x2x, CP => TRC, CR => n2024, LD => n746x0x, Q => n2080, QN => n2025); n2024 <= '1'; old_tbr_sig_regx1x : FDS2LP port map( D => old_tbr_sig745x1x, CP => TRC, CR => n2026, LD => n746x0x, Q => n2081, QN => n2027); n2026 <= '1'; old_tbr_sig_regx0x : FDS2LP port map( D => old_tbr_sig745x0x, CP => TRC, CR => n2028, LD => n746x0x, Q => n2082, QN => n2029); n2028 <= '1'; i_regx3x : FD1P port map( D => i773x3x, CP => TRC, Q => ix3x, QN => n2083); i_regx2x : FD1P port map( D => i773x2x, CP => TRC, Q => ix2x, QN => n2084); i_regx1x : FD1P port map( D => i773x1x, CP => TRC, Q => ix1x, QN => n2085); i_regx0x : FD1P port map( D => i773x0x, CP => TRC, Q => ix0x, QN => n2086); cnt_regx0x : FDS2LP port map( D => cnt716x0x, CP => TRC, CR => n2030, LD => n781x3x, Q => cntx0x, QN => n2087); n2030 <= '1'; cnt_regx1x : FDS2LP port map( D => cnt716x1x, CP => TRC, CR => n2031, LD => n781x3x, Q => cntx1x, QN => n2088); n2031 <= '1'; cnt_regx2x : FDS2LP port map( D => cnt716x2x, CP => TRC, CR => n2032, LD => n781x3x, Q => cntx2x, QN => n2089); n2032 <= '1'; cnt_regx3x : FDS2LP port map( D => cnt716x3x, CP => TRC, CR => n2033, LD => n781x3x, Q => cntx3x, QN => n2090); n2033 <= '1'; trans_reg_regx11x : FJK1P port map( J => n880, K => n2034, CP => TRC, Q => n2091, QN => n2035); n2034 <= '0'; trans_reg_regx10x : FDS2LP port map( D => trans_reg903x10x, CP => TRC, CR => n2036, LD => n880, Q => n2092, QN => n2037); n2036 <= '1'; trans_reg_regx9x : FDS2LP port map( D => trans_reg903x9x, CP => TRC, CR => n2038, LD => n880, Q => n2093, QN => n2039); n2038 <= '1'; trans_reg_regx8x : FDS2LP port map( D => trans_reg903x8x, CP => TRC, CR => n2040, LD => n880, Q => n2094, QN => n2041); n2040 <= '1'; trans_reg_regx7x : FDS2LP port map( D => trans_reg903x7x, CP => TRC, CR => n2042, LD => n880, Q => n2095, QN => n2043); n2042 <= '1'; trans_reg_regx6x : FDS2LP port map( D => trans_reg903x6x, CP => TRC, CR => n2044, LD => n880, Q => n2096, QN => n2045); n2044 <= '1'; trans_reg_regx5x : FDS2LP port map( D => trans_reg903x5x, CP => TRC, CR => n2046, LD => n880, Q => n2097, QN => n2047); n2046 <= '1'; trans_reg_regx4x : FDS2LP port map( D => trans_reg903x4x, CP => TRC, CR => n2048, LD => n880, Q => n2098, QN => n2049); n2048 <= '1'; trans_reg_regx3x : FDS2LP port map( D => trans_reg903x3x, CP => TRC, CR => n2050, LD => n880, Q => n2099, QN => n2051); n2050 <= '1'; trans_reg_regx2x : FDS2LP port map( D => trans_reg903x2x, CP => TRC, CR => n2052, LD => n880, Q => n2100, QN => n2053); n2052 <= '1'; trans_reg_regx1x : FDS2LP port map( D => trans_reg903x1x, CP => TRC, CR => n2054, LD => n880, Q => n2101, QN => n2055); n2054 <= '1'; trans_reg_regx0x : FDS2LP port map( D => trans_reg903x0x, CP => TRC, CR => n2056, LD => n880, Q => TRO, QN => n2102); n2056 <= '1'; go_reg : FDS2LP port map( D => xcellx170xU31xDATA2_0, CP => TRC, CR => n2060 , LD => xcellx170xU33xDATA2_0, Q => go, QN => n2103) ; TBRE_tri_enable_reg : FDS2LP port map( D => SFD, CP => TRC, CR => n2057, LD => n880, Q => n2104, QN => n2013); n2057 <= '1'; TBRE_reg : FDS2LP port map( D => xcellx170xU11xCONTROL2, CP => TRC, CR => n2058, LD => n880, Q => TBRE_Q817, QN => n2105); n2058 <= '1'; TRE_reg : FDS2LP port map( D => TRE897, CP => TRC, CR => n2059, LD => n790, Q => TRE, QN => n2106); n2059 <= '1'; delay_regx0x : FDS2LP port map( D => xcellx170xU29xDATA2_0, CP => TRC, CR => n2060, LD => xcellx170xU33xDATA2_0, Q => delayx0x, QN => n2107); t_pari_reg : LD4P port map( D => temp391, GN => TBRL, CD => n2060, Q => t_pari, QN => n2108); U695 : IVA port map( A => MR, Z => n2060); r107xU1_1_2 : HA1P port map( A => cntx2x, B => r107xcarryx2x, S => sum1616x2x, CO => r107xcarryx3x); r107xU1_1_1 : HA1P port map( A => cntx1x, B => cntx0x, S => sum1616x1x, CO => r107xcarryx2x); P3xadd_254xplusxU1_1_2 : HA1P port map( A => ix2x, B => P3xadd_254xplusxcarryx2x, S => ARG1440x2x, CO => P3xadd_254xplusxcarryx3x); P3xadd_254xplusxU1_1_1 : HA1P port map( A => ix1x, B => ix0x, S => ARG1440x1x, CO => P3xadd_254xplusxcarryx2x); end SYN;