Exams

Schedule

• Friday, Jan. 9, 2009, from 10:00 to 15:00, IT-226.
• Wednesday, Jan. 14, 2009, from 10:00 to 15:00, IT-226.
• Friday, Jan. 16, 2009, from 10:00 to 15:00, IT-226.
• Wednesday, Jan. 21, 2009, from 10:00 to 15:00, IT-226.
• Friday, Jan. 23, 2009, from 10:00 to 15:00, IT-226.

Registration is needed. This can be made by sending an e-mail to the lecturer.

Only one test can be made during the examination period.
Different dates are possible but should be agreed beforehand.

Consultations

• Thursday, Jan. 18, 2009, 15:00, IT-226.
• Tuesday, Jan. 13, 2009, 15:00, IT-226.
• Thursday, Jan. 15, 2009, 15:00, IT-226.
• Tuesday, Jan. 20, 2009, 15:00, IT-226.
• Thursday, Jan. 22, 2009, 15:00, IT-226.

Questions

I

1. Digital system, abstraction levels, and synthesis phases (based on X-, Y-design diagrams and design cube).
2. Modeling of discrete systems. Delta-delay based simulation engine in VHDL.
3. The needs and reasons for hardware description languages.
4. Various hardware description languages, their comparison.
5. Verilog - behavioral, dataflow, and structural styles. Differences from VHDL.
6. Design methodologies for digital systems and for System-on-Chip.
7. Concept of system; system level description languages.
8. Tasks in system level synthesis - clustering, optimizations, ...).
9. Transformations in synthesis of digital systems. Their effects on hardware and software implementations.
10. High-level synthesis, synthesis steps and methodology. Control and data flow graph.
11. Scheduling in high-level synthesis (ALAP, ASAP, AFAP scheduling algorithms).
12. Hu's algorithm for resource constrained scheduling (list based scheduling algorithms).
13. Resource allocation and binding in high-level synthesis.
14. Tasks in register transfer level synthesis - data and control part synthesis, retiming, pipelining.
15. Resource allocation and binding in register transfer level synthesis. Selection of architectural solutions.
16. Physical level synthesis. the main sub-tasks.

II

1. Behavioral description style in VHDL.
2. Dataflow description style in VHDL.
3. Structural description style in VHDL.
4. VHDL data types, objects, and predefined operators.
5. VHDL construction elements - entity and architecture, binding them.
6. VHDL construction elements - subroutines and packages, calling them.
7. Libraries in VHDL. Predefined libraries.
8. Process statement - activation, sensitivity.
9. Signal assignment, drivers, and delays. Resolved signals.
10. Sequential statements. Assert statement. Procedures.
11. Concurrent statements - assignments, processes, blocks, assertions.
12. Ports in entities and components. Direction and binding.
13. Regular structures and generate statements. Generics.
14. Configuration declarations.
15. Large project managing in VHDL. Test benches.
16. Synthesizable subset of VHDL - requirements and limitations.

Last modified 2008.12.15