Memory Cores

The aim of this project is to develop generic synthesizable memory cores
Most of the cores are synthesized on different FPGAs and gave good results.
If you have any comments please email me.
You can find the latest version of the cores in the opencores
To use these cores of for any licensing information please contact me and check the OpenIPCore site

• Dual Port Memory core.
• Generic Dual Port memory. vhdl code Latest release
• Single clock for read and write with reset. core description,  vhdl code  ,  download , download old complete version
• Two different clock for read and write without reset. core description, vhdl code  , verilog code ,  download
• Single Port Memory core
• Generic Single Port memory. vhdl code Latest release
• Single port memory core. core description, vhdl code  ,  download , download old complete version
• FIFO buffer core.
• Synchronous FIFO, Single clock for both read and write. core description, vhdl code , Schematic ,  download
• Schematic generated by synplify tool of some old fifo architectures by Joe Zott , fifo_v4 , fifo_v5, fifo_v6
• Synchronous FIFO, different clocks for both read and write. core description, vhdl code  ,  download
• Asynchronous FIFO . core description, vhdl code  ,  download ,  CVS "latest version" ... to come soon
• Look-up table core. core description, vhdl code  ,  download
• Memory package.  vhdl code  , download
• You can download memory cores from OpenCores CVS
• Memory cores 1 Old package but it is good to look at them.
• Memory cores 2

Memory cores 2 package contents

Please if you have any extra cores or suggestions send me an email.

Notes:

Links to other memory cores and tips

• IDT.com the source for many FIFO and dual port memory chips
• FIFO products at TI
• VHDL FIFO core
• VHDL FIFO core based on register file
• DesignWare Memory: FIFO Components List