Rules for Actuals
and Locals

Locals are defined as the ports of the component. VHDL has two restrictions on the association of locals with actuals. First, the local and actual must be of the same data type. Second, the local and actual must be capable of being readable and/or writable. A local of mode IN can only be associated with an actual of mode IN. Ports of mode OUT behave similarly. A local INOUT port is generally associated with an INOUT or OUT actual.