This slide shows an example of the FOR-scheme. While this is a
simple example, far more complex designs can be generated.
The code generates an array of AND gates. The and_gate
component used previously is employed here. In this case, the
GENERATE statement has been named G1 and is instantiating an
array of 8 and_gate components. The PORT MAP statement maps the
interface of each of the 8 gates to a specific element of the signal
vectors. The leftmost and_gate has the seventh element of
signals S1, S2, and S3 mapped to its interface.
This continues to the last and_gate of the array (rightmost)
where the zeroth element of S1, S2, and S3 is
mapped to its interface.
