Delta Delay

VHDL encourages the designer to describe the hardware at whatever level is appropriate. Timing and delay information may not always be available when a system is first described in abstract forms. However, useful system simulations may be made at such levels so that models with no timing information must be supported.

VHDL maintains its sequential mode and concurrent mode semantics by the use of delta delay. A delta is essentially an infinitesimal, but quantized, unit of time. When a signal assignment is made with no explicit delay (i.e. no after clause), a delay of one delta cycle is assumed. This maintains the semantics that every signal assignment statement is actually the scheduling of a future value to be assigned to the signal, and the simulation cycle described earlier will function correctly. That is, all active processes continue to execute until they all suspend at wait statements at which point time advances (by either one delta cycle or by the minimum simulation time required for any signals to be able to assume new values).