The configuration construct allows the designer to choose exactly what
model a component will use. During the design process, various parts
of the design can be parceled off to various teams or people. VHDL
supports this "divide and conquer" strategy. However, once all the
pieces have been developed, they must be brought together in a
rational manner. Architectures may be developed without knowing the
exact details of the components. Therefore, the exact component model
must be chosen when compilation occurs. The configuration statement
allows the designer to choose the component model appropriate for the
design.
The configuration statement must account for many differences between
the entity and the component. First, the entity name may be different
than the component name. Second, the entity declaration may have more
ports that the component declaration. A more generic part may have
been developed with additional ports to keep the parts count down.
However, these extra ports cannot be ignored. Finally, the ports of
the entity may have different names than those on the component
declaration. These different port names must be matched.
