Without delta delay, the order of execution in this series of logic is
uncertain. While the end result is the same, the extra pulse
generated could cause other logic to trigger unexpectedly. Without a
clear order of execution, VHDL would be a poor language for simulation.
The solution, in this case, is to make zero delay devices have an
equal, but infinitesimal, delay, i.e. a delta cycle delay. The
delta delay, as mentioned before, does not advance simulation time
(i.e. no seconds, or ms, or ns, etc., are advanced). The delta delay
is a scheduling device so that the simulator provides consistent and
predictable behavior for models without specified delays.
