This is the same example as before. However, each signal assignment
will incur a one delta cycle delay.
The one to zero transition in IN occurs on the inverter just as
before. A is then scheduled to be updated one delta cycle in
the future. On the next delta cycle, A is updated, and now both
the NAND and AND devices are evaluated concurrently and any resulting
signal assignments will result in signals B and C being
assigned new values one delta cycle in the future. When B and
C change in the next delta cycle, however, the change in
B triggers a second evaluation of the AND gate which results in
an assignment of zero to C. C reaches this final value
on the subsequent delta cycle.
[Perry94], pp. 22-24.
