This figure captures the main features of a complete VHDL model. A
single component model is composed of one entity and one or many
architectures. The entity represents the interface specification (I/O)
of the component. It defines the components external view, sometimes
referred to as its "pins".
The architecture(s) describe the function or composition of an entity.
There are three general types of architectures. One type of
architecture describes the structure of the design (right hand side)
in terms of its sub-components and their interconnections. A key item
of a structural VHDL architecture is the "configuration statement"
which binds the entity of a sub-component to one of several
alternative architectures for that component.
A second type of architecture, containing only concurrent statements,
is commonly referred to as a dataflow description (left hand side).
Concurrent statements execute when data is available on their inputs.
These statements can occur in any order within the architecture.
The third type of architecture is the behavioral description in which
the functional and possibly timing characteristics are described using
VHDL concurrent statements and processes. The process is a concurrent
statement of an architecture. All statements contained within a
process execute in a sequential order until it gets suspended by a
wait statement.
Packages are used to provide a collection of common declarations,
constants, and/or subprograms to entities and architectures.
Generics provide a method to communicate static information to a
architecture from the external environment. They are passed through
the entity construct.
Ports provide the mechanism for a device to communication with its
environment. A port declaration defines the names, types, directions,
and possible default values for the signals in a component's interface.
Implicit in this figure is the testbench which is the top level of a
self-contained simulatable model. The testbench is a special VHDL
object for which the entity has no signals in its port declaration.
Its architecture often contains constructs from all three of the types
described above. Structural VHDL concepts are used to connect the
model's various components together, Dataflow and behavioral concepts
are often used to provide the simulation's start/stop conditions, or
other desired modeling directives.
This slide will be used again at the end of this module as a review.
