In review, the final result for both of these implementations is the
same. However, the example using variables reached its
quiescent state immediately after the change in a rather than 2
delta cycles later, although the order of the two assignment
statements became important. In addition, variables have less
simulator overhead because there are no waveforms associated
with them. In conclusion then, both signals and
variables serve their purposes in VHDL well, but, although
signals can often be used in place of variables, that
practice leads to unnecessary simulation (and/or delta delays) and
added simulator overhead.
