A component represents an entity/architecture pair. A component
instantiation statement defines a subcomponent of a design and
associates signals with the ports of that subcomponent and
associates values with generics of that subcomponent. An analogy to
actual hardware would be the plugging of a hardware component into a
board and making the electrical connections between the pins of the
component and the circuit board.
In VHDL, the instantiation of components requires two mechanisms, the
Component Declaration and the Component Instantiation.
These will be shown in the subsequent slides.
