`timescale 1ns /1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    22:09:09 12.10.2010
// Design Name: 
// Module Name:    ALL_IN_ONE_test
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ALL_IN_ONE_test( );

	parameter k = 2;
	parameter levels = 2;
	parameter p_size = k*k + 4*k + 1;
	reg [3:0] func;
	reg clk; 
	
	integer i,j,c0,c1,c2,c3;

reg 	[(2*k*p_size)-1:0]	in; 
reg 	[(2*k)-1:0]				sin;
wire 	[(2*k*p_size)-1:0]	out;
wire 	[(2*k)-1:0]				sout;

/******************************************************************************************/


initial 

begin 
	clk = 0;
	
	sin = 4'b 0000;
	
		func = 3;
		$monitor ("##########################################  Function: %d  ##############################################",func);
		c0 = 0;
		c1 = 0;
		c2 = 0;
		c3 = 0;
		i = 0;
				
		while ((c0 < 100) | (c1 < 100) | (c2 < 100) | (c3 < 100)) begin
			i = i + 1;			
			@(negedge clk) //will wait for next negative edge of the cl
			begin
				if ((sout[0] == 0) ) begin
						if (i % 4 == 0) in[12:0] = 13'b0000000111100;
					if (i % 4 == 1) in[12:0] = 13'b0101010111110;
					if (i % 4 == 2) in[25:13] = 13'b1111000111101;
					if (i % 4 == 3) in[25:13] = 13'b1010010111111;
						if (c0 < 100) c0 = c0 + 1;
				end	//if
				if ((sout[1] == 0)) begin
						if (i % 4 == 0) in[25:13] = 13'b1111000111101;
					if (i % 4 == 1) in[25:13] = 13'b1010010111111;
					if (i % 4 == 2) in[12:0] = 13'b0000000111100;
					if (i % 4 == 3) in[12:0] = 13'b0101010111110;
						if (c1 < 100) c1 = c1 + 1;
				end	//if
				if ((sout[2] == 0)) begin
						if (i % 4 == 0) in[38:26] = 13'b0101000111110;
					if (i % 4 == 1) in[38:26] = 13'b0000010111100;
					if (i % 4 == 2) in[51:39] = 13'b1010000111111;
					if (i % 4 == 3) in[51:39] = 13'b1111010111101;
						if (c2 < 100) c2 = c2 + 1;
				end	//if
				if ((sout[3] == 0)) begin
						if (i % 4 == 0) in[51:39] = 13'b1010000111111;
					if (i % 4 == 1) in[51:39] = 13'b1111010111101;
					if (i % 4 == 2) in[38:26] = 13'b0101000111110;
					if (i % 4 == 3) in[38:26] = 13'b0000010111100;
						if (c3 < 100) c3 = c3 + 1;
				end	//if
			end
		end
	end	

always 
	#1 clk = !clk; 
	
	always @(in | sin)
	begin
		$monitor ("INPUT: %g\t %b %b %b %b  || %b  || %d | %d | %d | %d | ", $time,in[12:0],in[25:13],in[38:26],in[51:39],sin,c3,c2,c1,c0);
	end
	
	always @(out | sout)
	begin
		$monitor ("OUTPUT: %g\t %b %b %b %b  || %b ", $time,out[12:0],out[25:13],out[38:26],out[51:39],sout);
	end

//Main_module(INPUTA,INPUTSA,Func_num,Clock,OUTPUTA,OUTPUTSA);		
// BF_Network(INPUTA,INPUTSA,Clock,OUTPUTA,OUTPUTSA);

//BF_Network DUT (in,sin,clk, out,sout ); 
Main_module DUT (in,sin,func,clk, out,sout ); 


	
	
endmodule