LAB in Chip Desighn 203.4260 203.3260 (Yosi Ben Asher)

In this lab we design and build a hardware project that is related to embedded systems and SOC (System on a Chip). The first part of the course covers the issue of hardware programming using the Verilog language. The main task of this course is to build some components for embedded systems. The project usually involve algorithmic concepts as well as practical aspects of embedded systems.

Topics:


- Basic hardware components.
- Combinatorial circuits and sequential circuits as finite state machines.
- Verilog programming.
- Testbench and simulations.
- Blocking and non-blocking assignments.
- Field programable gate arrays (FPGAs).
- Using FPGA synthesis tools (the ISE webpack)
- Signal-processing and Algorithms used in SOC or parallel programming using multicores.
- Project discussions.

PLS. come every one/two weeks to my office to monitor your progress

Download XILINX's ISE/VIVADO OR Altera's Quartus tool for FPGA synthesis (both syntehsis and simulations)

You may also Download Icarus Verilog to run the testbench

A partner requested for:

Slides :

  • PACOBLAZE a clone of PICOBLAZE (for projects that uses picoblaze cpu)
  • a Verilog tutorial part 1 (from the web)
  • a Verilog tutorial part 2 (from the web)
  • a Verilog tutorial part 3 (from the web)
  • another Verilog tutorial
  • Slides explaining the difference between blocking and non blocking assignments
  • A paper explaining the difference between blocking and non blocking assignments
  • Introduction to Verilog from Columbia University
    Ãâó: http://www1.cs.columbia.edu/~sedwards/classes/2002/w4995-02/verilog.pdf
  • ICARUS Verilog
  • ICARUS Verilog windows instalation
  • ICARUS Verilog example 1 for a testbench

    Projects :

  • 2007 project Extended Booth algorithm
  • 2008 project Shared Memory module
  • 2009 project Tiny CPU Generator
  • 2010 project Shared memory multicore
  • 2011 project Butterfly FFT
  • 2013 project Parallel Viterbi decoder

    Reading: The Verilog Hardware Description Language by Thomas and Moorby, Fourth Edition Kluwer Academic.
    HDL Chip Design : A Practical guide for Designing, Synthesizing and Simulating ASICs and FPGAs using VHDL or Verilog, by Douglas J. Smith Doone Publications