Design a 4-Bit ALU

EE481 Logic Design Lab
Fall 2003, Lab #9

Experiments

  1. Design and implement the following circuit using a MACH111SP CPLD device (CPLD, Vantis ). You need to use Synario schematic entry software to simplify your design task.

  2. C0 is the carry out from A+B.
  3. Include logic design equations for your design.
  4. Count total number of wires used for CPLD design.
  5. Measure the average current that the CPLD uses without using the LEDs.
  6. Are there any cost savings in using CPLD? (Assume that CPLD chip costs $4 and TTL chip costs $.50).

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