EE481 
Logic Design Lab

Fall 2003 Syllabus

Course Information

Instructor: 
Office: 
Email: 
URL: 
Lecture: 
Lab Room: 
Lab Instr.: Wed
Lab Instr.: Thu
Required Text: 
Prerequisites:

Dr. Mike Lhamon 
Anderson Hall (FPAT) 565 
melham01@engr.uky.edu 
http://www.engr.uky.edu/~melham01 
Fridays 1:00-1:50pm in White Hall 215 or FPAT581  
FPAT581 
Gohar Saeed  
Gohar Saeed  
TTL DataBook and your EE280 book  
EE 222, EE 280, and a 'C' or better in EE 221.

Fall Schedule 2003:

Office Hours:
Fridays: 2:00-3:00
and by appointment via E-mail.
Class Times:
EE481 Logic Design Lab, Room 215 White Hall, Fridays 1:00-1:50
Below is a tentative list of experiments for this course. Deviations from this schedule will be announced in class and on the course web page.


In lieu of students buying a text book you need to buy a parts kit for the lab.  The kit must contain large breadboard wire cutters, wire strippers and standard 5v TTL ICs.

Week
8-27
1-1
9-8
9-15
9-22
9-29
10-6
10-13
10-20
10-27
11-3
11-10
11-17
11-24
12-1
12-8
12-15

Lab 
---  
1
1  
2  
3  
4  
P1
5  
6
7  
8  
P2  
9  
---
Prj
Prj
---  

Experiment 

Combinational Circuits
Combinational Circuits (con't)
Muxtiplexers & Demux.
Adders & BCD Addition  
Flip Flops / Hazards  
Lab Practical Exam #1  
Printer Port Counter  
PAL & Counters
Mealy & Moore Machines  
Bus and LCD Module Interfacing
Lab Practical #2
Complex PLD Experiment
Free lab time for all sections
Project #1  
Project #1 con't
Finals, No final in EE481  

Notes 


Finish up Lab #1.



Study Hard
Computer Control via Parallel Port
Sync/Async. Counters
Synchronous State Machines
Microprocesser Bus Control
Study
Lab to be determined
Thanksgiving Holiday
Lets put it all together!
Hand in your project reports
Return your parts!  
Make certain that your web page viewer is wide enough to display the table properly. All of the rows should line up perfectly.

Course Outcomes and Goals

1. Ability to synthesize and analyze combinatorial digital logic circuits using discrete logic circuits, proms, encoders/decoders and programmable array logic (PALs).

2. Ability to synthesize and analyze sequential digital logic circuits using discrete logic circuits, proms, encoders/decoders and programmable array logic (PALs).

3. Ability to read and understand technical specifications and apply to current design.

4. Ability to formulate engineering problem and to solve them using a top-down approach.





Aug. 27, 2003