Introduction to Synthesis using VHDL

Outline

Why HDLs

Evolution of design capture methods

Problem

HDLs vs Schematics

Advantages of HDLs

The first three can be addressed by

But schematics are tuned to bottom-up methodologies!

fact:: Nat -> Nat

fact 1     =  1 

fact (x+1) = (x+1) * fact (x)

Programs vs Circuits

Algorithm

Discrete computations

Non-terminating procedures

f:: Int -> Int

f x = f(x) + 1

Termination is undecidable!

Fixed Point, Domain Theory

General Recursion is a sledgehammer!

Recursion vs Induction

datatype Nat

   Zero:: Nat

   Succ:: Nat -> Nat

Example:

3 = Succ 2 

  = Succ (Succ 1) 

  = Succ (Succ (Succ Zero))

Inductive definitions

fact 1       = 1

fact (x + 1) = (x+1) * rec x 

Discrete computations > Inductive definitions

Assuming appropriate operations, all inductive computations can be mapped to digital circuits:

Expansion in space

datatype Bus (n::Nat,a)

   Nil:: Bus (0,a)

   Cons:: a (Bus (n,a)) -> Bus (n+1,a)

abbreviated:			[a]#n

rowr:: ((a,b)->(c,a)) a [b]#n->(a,[c]#n)      

rowr f r Nil         -> (r,Nil) 

rowr f r (Cons a as) -> let (rx,bs) <- rec as

                             (b,r1)<-f (rx,a)

                        in (r1,Cons b bs)

zip:: [a]#n [b]#n -> [(a,b)]#n

zip Nil Nil                -> Nil

zip (Cons a as) (Cons b bs)-> Cons (a,b) (rec as bs)

rc_adder::[Bit]#n [Bit]#n Bit -> (Bit,[Bit]#n)

rc_adder as bs cin -> rowr full_adder cin (zip as bs)

Induction into Iteration

Tail recursive form

fact_tr N = fact1 N 1

fact1 1 y = y

fact1 x y = let y1= x * y

                x1= x-1

            in fact1 x1 y1

Iterative form

x:=N; y:=1;

while x>=1 do

   {y:= x* y; x:= x - 1}

Not all algorithms can be transformed into tail recursive form!

Comparing fact and fact_tr

fact 1     =  1 

fact (x+1) = (x+1) * fact (x)

fact_tr N = fact1 N 1

fact1 1 y = y

fact1 x y = fact1 (x * y) (x-1)

       = 3 * (2 * fact 1)

       = 3 * 2 * 1

fact_tr 3 = fact_tr 3 1  

          = fact_tr 2 (1*3) 

          = fact_tr 1 (1*2*3)

          = 1 * 2 * 3

What we have achieved so far

A hierarchy of behavior description styles (abstract -> concrete):

A gentle introduction to VHDL

What is VHDL

What is then synthesizable VHDL

Chronology

VHDL or Verilog

Design Organization

Entity specifications

entity NAND2 iS  - case insensitive

   port (A,B: in BIT;

         Z: out BIT);

end NAND2

Ports

Generics

Architectures - 1

Structural

architecture STRUCTURAL of NAND2 is

   signal I: Bit;

   component AND_2 -- Not needed in VHDL-92

      port(I1,I2: in Bit; O1: out BIT);

   end component;

   component INVERT

      port(I1: in Bit; O1: out Bit);

   end component;

begin

   U0: AND_2 port map (I1,I2,I); --positional

   U1: INVERT port map (I1=>I,O1=>Z);

end STRUCTURAL

;

Architectures - 2

Dataflow

architecture DATAFLOW of NAND2 is

begin

   z = A nand b;

end DATAFLOW

Behavioral

architecture BEHAVIORAL of NAND2 is

begin

   process(A,B)

   begin

     if (A='1') and (B='1') then

        Z<='0';

     else

        z<='1';

     end if;

   end process;

end BEHAVIORAL; 

Architecture organization

Declarations

Concurrent statements

Package Organization

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