FOR-Scheme Example

-- this uses the and_gate component from before
ARCHITECTURE test_generate OF test_entity IS
    SIGNAL S1, S2, S3 : BIT_VECTOR (7 DOWNTO 0);
BEGIN
   G1 : FOR n IN 7 DOWNTO 0 GENERATE
    and_array : and_gate
       GENERIC MAP (2 ns, 3 ns)
       PORT MAP (S1(n), S2(n), S3(n));
   END GENERATE G1;
END test_generate;