Port
Formal Definition
A channel for dynamic
communication between a block and its environment.
Simplified Syntax
port ( port_declaration,
port_declaration, &ldots;);
-- port declarations:
port_signal_name : in port_signal_type
:= initial_value
port_signal_name : out port_signal_type
:= initial_value
port_signal_name : inout port_signal_type
:= initial_value
port_signal_name : buffer port_signal_type
:= initial_value
port_signal_name : linkage port_signal_type
:= initial_value
Description
Ports are a part of the
block interface: external -
if defined by a design entity, or internal - if defined by a block
statement. Each element listed in a port interface list declares a
formal port, which provides a channel for dynamic communication
between a block and its environment.
In practice, ports are most
often used in entities and components, where they serve for declaring
interface signals of a design entity (system design) or component, respectively.
In both cases, each interface element is a signal. It can be preceded
by a keyword signal. After
the signal's name, a mode is specified. The mode declares the
direction of data flow through the port. There are five modes
available in VHDL for ports:
-
in input port. A variable or
a signal can read a value from a port of mode in,
but is not allowed to assign a value to it.
-
out output port. It is
allowed to make signal assignments to a port of the mode out,
but it is not legal to read from it.
-
inout bi-directional port.
Both assignments to such a port and reading from it are allowed.
-
buffer output port with read
capability. It differs from inout
in that it can be updated by at most one source, whereas inout
can be updated by zero or more sources.
-
linkage . The value of the
port may be read or updated, but only by appearing as an actual
corresponding to an interface object of mode linkage.
If a port is declared with a reserved word bus,
then the signal declared by that port is a guarded signal of signal
kind bus.
A port can be assigned a default value, which is specified by an
expression evaluating to the same type as the port itself.
Examples
Example 1
entity Mux8to1 is
port (
Inputs : in
Std_Logic_Vector(7 downto 0);
Select_s : in
Std_Logic_Vector(2 downto 0);
Output : out Std_Logic
);
end Mux8to1;
Entity of a multiplexor 8-to-1 contains three ports: eight data
inputs (specified as a vector), address inputs and one output.
Example 2
component MemDev is
port(
Data : inout
Std_Logic_Vector(7 downto 0);
Addr : in
Std_Logic_Vector(9 downto 0);
NotCS : in Std_Logic;
RdNotWr : in Bit
);
end component MemDev;
Memory device is specified here as a component with four signals:
data is a bi-directional data bus, address is a ten-bit input, and
NotCS and RdNotWr are single inputs signals. Note that the keyword is
in the header can be used in VHDL 93 only (in VHDL 87 it must be omitted).
Important Notes
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