Using Xilinx Foundation Series Software:

1. In the Project Manager window, select HDL Editor . The HDL Editor window will appear.
   
   
   
   
2. Select Use HDL Design Wizard, and click OK.
   
   
   1. The HDL Design Wizard is now active, and will help you start your design. To begin select Next.
      
      
   2. We will be using VHDL, so select VHDL and click Next.
      
      
   3. Type a name for the design you are going to create, ex. XORer. Click Next.
      
      
   4. You must now assign all the ports in your design. Click New.
      
      
      
      
   5. Type a name for the port in the Name box, ex. X1, then set the Direction of the port, ex. Input. Click New to Add another port, continue until ALL inputs and outputs have been defined. Click Finish.
      
      
3. The HDL Editor window will now appear with the Design Wizards input and output code already defined. Scroll down to the place in the code that specifies "-- <<Enter Your Statements Here>>" in green text. This is where you will define the function of the Module. Delete the green text and in its place type the function of the logic that you are implementing. ex. For the XORer you would type "Y <= X1 xor X2;" The exact syntax and semicolon are important.
   
   
   
   
4. In the File menu, select Save. This will store your code.
   
   
   

   	In the Synthesis menu, select Check Syntax. This will check your code for syntax errors. Click OK if the Syntax Check is successful.
   	In the Synthesis menu, select Synthesize. This synthesizes your code into a logic level design. Click OK if the code synthesized correctly.
   	In the Project menu, select Create Macro. This creates a symbol that can be used in the Schematic Entry window for functional simulation. Click OK if the symbol was created correctly.

   
   
   
5. You have now completed the VHDL portion of the process. In the SC Symbols toolbox in the Schematic Editor window there should be a part available that matches the name you gave to your VHDL file ex. XORER. You can place this part in any schematic and you can simulate it by using the SIM Funct window combined with inputs and outputs or probes.

See Xilinx Foundation Series: Schematic Entry

Xilinx Foundation Series: Functional Simulation in the Waveform Viewer

Xilinx Foundation Series: Observation of Functional Simulation within the Schematic Editor

Download a Microsoft Word 95 7.0 Text only printable version of these instructions: VHDLMacroGeneration.doc

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