What's New

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1. "Free Stuff" section updated with
       - free waveform viewer
       - links to Icarus Windows binaries.
       - link to Verilogger Linux binary
       - Link to free Verilog models from Young Engineering
2. 2 links to QA pages and new questions are added in "Technical Questions asked in Interviews" page.
3. "Writing Efficient Testbenches" added in Technical Papers section.
4. VCD scripts link added to "Productivity Tools" Page.
5. Verilog Source Navigator added to "Productivity Tools" Page.
6. HDLMaker added to "Productivity Tools" Page.
7. A new section of Cool links added to "Productivity Tools" Page.
8. A new section on Language Interfaces added to "Productivity Tools" Page.
9. A free Verilog code coverage tool added to "Productivity Tools" Page.

1. 6 new questions are added in "Technical Questions asked in Interviews" page.
2. "Writing Efficient Testbenches" added in Technical Papers section.
3. A free timing diagram tool added to "Productivity Tools" Page.
4. A free Verilog code coverage tool added to "Productivity Tools" Page.

1. Perl interface to speed up verification times with SimWave added in "Productivity Tools" page. This replaces earlier C version.
2. ScriptSim : Bring the power of Perl/Tk and Python/Tk to your Verilog?simulations added in "Productivity Tools" page.
3. System Verilog Specifications added to "Technical Papers" section.

1. Four new questions added in "Interview Questions" page.

1. Icarus added in Free Stuff section.
2. John Sanguinetti's course added in Free Stuff section.

1. Whole site is reformatted for better navigation. Fixed bad links.
2. "Tools" section is updated with new links to
   Open Verification Library (OVL), Jeda, OpenVera, TestBuilder, OpenCores.

1. Cliff Cummings's 7 papers added in  "Papers" section
2. Ben Cohen's SNUG 2001 Presentation on "Component Verification by example" added in "Papers" section.
3. Vincenzo Liguori's Free VHDL to Verilog RTL translator added in "Free Stuff" section.
4. Unusual Clock Dividers by Peter Alfke added in "Papers" section.
5. Link to Jeff Solomon's Synopsys Plus Perl (SPP) updated in "Tools" section.
6. Sequence Detector image fixed in "Interview Questions" page.

1. Cliff Cummings's paper on Nonblocking Assignments added in "Papers" section
2. One more site added to free cores listing on "Free Stuff" page .
3. Free Timing Diagram Tool added on "Free Stuff" page
4. ScriptEDA added in "Tools" page
5. Many old links fixed.

Version 2.0                     Updated 06/16/2000

1. "What's New" page added to Verilog Center.
2. Utku Ozkan's "C-interface to speed up verification times with SimWave" updated.
3. Motorola's Semiconductor Reuse Standards added in "Technical Papers" section.
4. List of sites providing free IP cores added in "Free Stuff" section.
5. Links to Emacs modes fixed in "Productivity Tools" section.