Technical Papers

• Verifying functionality is simply not enough : Rajesh Bawankule (DVCon 2013)
• Speed up Verilog Simulations by 10-100X without spending a penny.: Rajesh Bawankule
  DvCon Paper        presentation slides      EEDesign article about this paper.
  
• Writing Efficient Testbenches: Mujtaba Hamid, Xilinx
• System Verilog (v3.0) Specifications. Other related papers  

  Cliff Cumming's Papers

• RTL Coding Styles that yield Simulation and Synthesis Mismatches
• Coding and Scripting Techniques for FSM designs with Synthesis-Optimized, Glitch-Free outputs
• Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!
• Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs
• Correct Methods For Adding Delays to Verilog Behavioral Models
• Verilog-2001 Behavioral and Synthesis Enhancements
• "full_case parallel_case", the Evil Twins of Verilog Synthesis
  
  
• Ben Cohen's SNUG 2001 Presentation + Verilog Code + VHDL approaches on Component Verification by example using transaction based methods
  
• Unusual Clock Dividers
  An application note by Peter Alfke of Xilinx describing how to divide clocks by 1.5, 2.5, 3, and 5 with a 50% duty-cycle output. (other Xcell articles)

• The Ten Commandments of Excellent Design : Peter Chambers, Engineering Fellow VLSI Technology (VHDL Examples)
• Xilinx Design Reuse Methodology for ASIC and FPGA Designers

An Addendum to the Reuse Methodology Manual for System-On-Chip Designs
• Incremental HDL Synthesis and Guided P&R for Xilinx FPGAs:

An Application note by Stuart Clubb 
• Verilog Technical Tidbits : A good paper on how to write code, state machines. 
• Simulation Speed in HDLs : John Sanguinetti 
• Regression Testing During the design process : John Sanguinetti & David Manley 
• Execution of always block :  John Sanguinetti 
• RAM modelling in Verilog: John Sanguinetti & Farhad P. Sunavala 
• Verilog - accelerating digital design :Gerard M. Blair  (pdf version) 
• Verilog Code writing Guidelines :Rajesh Bawankule 

• VHDL & Verilog Compared and Contrasted : Douglas J. Smith 
• Verilog Won & VHDL Lost? -- You Be The Judge! : John Cooley
• Verilog vs. VHDL : John Sanguinetti 

Papers on Metastability

• The University of Queensland Electrical and Computer Engineering Notes 
• Keep metastability from killing your digital design : Debora Grosse
• Synchronizing asynchronous signals causes metastability, which makes it difficult to iron out the bugs during system test. Paying close attention to the synchronizer and some metastability equations can help you avoid the pitfalls. 
• Metastable Response in 5-V Logic Circuits
• This document describes metastable response in digital circuits. After a definition of a metastable state, a test circuit is provided, its responses analyzed, and test results given. Examples show the influence of metastability on the response of asynchronous circuits and measures for improving reliability are assessed. 
• Summary: Metastability is unavoidable in asynchronous systems.   However, using the formulas and test measurements supplied here, designers can calculate the probability of failure.  Design techniques for minimizing metastability are also provided. 
• Xilinx Application Note by P. Alfke and B. Philofsky.   Description of metastable states, measurement techniques, tables of metastable parameters, and a summary graph. 
• "Metastability Recovery in Xilinx FPGAs," Xilinx Corp. 
• UltraLogic/PLDs Section Contents and Abstracts. Are Your PLDs Metastable? This application note provides a detailed description of the metastable behavior.